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ADT7482
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14
acknowledge. The master then takes the data line low during
the low period before the tenth clock pulse, then high during
the tenth clock pulse to assert a stop condition.
Any number of bytes of data can be transferred over the
serial bus in one operation, but it is not possible to mix read
and write in one operation because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation. In the case of the
ADT7482, write operations contain either one or two bytes,
while read operations contain one byte.
To write data to one of the device data registers or to read
data from it, the address pointer register must be set so that
the correct data register is addressed. The first byte of a write
operation always contains a valid address that is stored in the
address pointer register. If data is to be written to the device,
the write operation contains a second data byte that is written
to the register selected by the address pointer register.
This procedure is illustrated in Figure 16. The device
address is sent over the bus followed by R/W
 set to 0. This
is followed by two data bytes. The first data byte is the
address of the internal data register to be written to, which
is stored in the address pointer register. The second data byte
is the data to be written to the internal data register.
Figure 16. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
1
SCLK
SDATA
0
0
1
1
0
0
D7    D6   D5   D4    D3   D2    D1    D0
ACK. BY
ADT7482
START BY
MASTER
1
9
1
ACK. BY
ADT7482
9
D7    D6    D5   D4    D3   D2    D1    D0
ACK. BY
ADT7482
STOP BY
MASTER
1
9
SCLK (CONTINUED)
SDATA (CONTINUED)
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA BYTE
R/W
Figure 17. Writing to the Address Pointer Register Only
1
SCLK
SDATA
0
0
1
1
0
0
D7    D6    D5    D4    D3    D2    D1    D0
ACK. BY
ADT7482
STOP BY
MASTER
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
1
9
ACK. BY
ADT7482
9
R/W
Figure 18. Reading Data from a Previously Selected Register
1
SCLK
SDATA
0
0
1
1
0
0
D7    D6    D5    D4    D3    D2    D1
D0
NO ACK.
BY MASTER
STOP BY
MASTER
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE FROM ADT7482
1
1
9
ACK. BY
ADT7482
9
R/W
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